1. Field of the Invention
The present invention relates to a clock signal feeding circuit that feeds clock signals to a synchronous semiconductor logic circuit.
2. Description of the Related Art
A logic circuit of a system large-scale integrated circuit (LSI), which is used in a central processing unit (CPU) or in a digital signal processor (DSP) and the like, is typically a synchronous circuit that controls operation of each logic circuit block synchronously with common clock signals. A synchronous circuit consists of a plurality of flip-flops (FFs) that synchronize the transmitting and receiving of data between logic circuit blocks with clock signals, and a clock signal feeding circuit that feeds clock signals to these FFs.
FIG. 2A is a circuitry diagram and FIG. 2B is a signal timing chart. FIGS. 2A and 2B illustrate a portion of a clock signal feeding circuit in a conventional logic circuit.
As shown in FIG. 2A, the clock signal feeding circuit feeds clock signals CKs, which have been inputted into an input terminal 3, synchronously to a FF1 and a FF2 that are provided at input and output sides of a logic circuit block LB, respectively.
The clock signal feeding circuit comprises the input terminal 3, a clock signal line 4 connected to the input terminal 3, and delay buffers 5 and 6. The delay buffer 5 is provided on the clock signal line 4, downstream of a branch point 41, and feeds clock signal CK1 to a clock terminal C of the FF1. The delay buffer 6 is provided on the clock signal line 4, downstream of a branch point 42, and feeds clock signal CK2 to a clock terminal C of the FF2. The clock signal CK1 is fed to the FF1 provided close to the input terminal 3, via the branch point 41 and delay buffer 5. The delay buffer 5 consists of four cascaded buffers 5a through 5d. The clock signal CK2 is fed to the FF2 provided away from the input terminal 3, via the branch point 42 and delay buffer 6. The delay buffer 6 consists of three cascaded buffers 6a through 6c. 
Each of the buffers 5a through 5d and 6a through 6c is formed from two serially-connected inverters, and is designed such that propagation delay time for each clock signal is constant. The number of the buffers inserted between the branch points 41, 42 of the clock signal line 4 and the clock terminal C of the FF1 and the FF2 is selected such that the clock signals CK1 and CK2 are synchronized at the clock terminal C of each FF1 and FF2.
The operation will be described below.
As FIG. 2B shows, the clock signal CK inputted at the input terminal 3 is fed to the clock terminal C of the FF1 as the clock signal CK1 via the clock signal line 4 and the delay buffer 5, after a predetermined delay time. Similarly, the clock signal CK is fed to the clock terminal C of the FF2 as the clock signal CK2 via the clock signal line 4 and the delay buffer 6, after a predetermined delay time. In this manner, the clock signals CK1 and CK2 are fed to the FF1 and FF2, respectively, in a substantially synchronized manner.
A data signal DT1, sent from a preceding logic circuit block (not shown) to a data terminal D of the FF1, is latched by the FF1 at a rise edge A of the clock signal CK1 and outputted from an output terminal Q as a data signal DT2. A data signal DT2, outputted from the FF1, is fed to the logic circuit block LB where predetermined logic operations are processed. After processing time TP has elapsed, a data signal DT3 representing the operation result is outputted and then inputted to the data terminal D of the FF2.
The data signal DT3, inputted into the FF2, is latched by the FF2 at a next rise edge B of the clock signal CK2 and outputted from an output terminal Q as a data signal DT4. The data signal DT4, outputted from the FF2, is fed to a subsequent logic circuit block (not shown).
The logic operation processing is conducted at each logic circuit block during each cycle of the clock signal CK, and the operation result is fed to the subsequent logic circuit block synchronously with the clock signal CK. Assuming that the cycle time of the clock signal CK is denoted by TC and the maximum processing time of the logic circuit block is denoted by TP, the margin of time TM of the operation in the logic circuit can be represented as TM=TCxe2x88x92TP.
Because the clock signal feeding circuit is structured such that the clock signals CK1, CK2 and the like are fed to the FF1, FF2 and the like synchronously, each logic circuit block can be designed simply and operation of the entire logic circuit becomes stable.
However, conventional clock signal feeding circuits have the following problems.
In each logic circuit block, data signals are inputted or outputted by clock signals that are fed synchronously in a constant cycle. Accordingly, each logic circuit block must be designed such that, even under the worst conditions within a guaranteed operating extent, the maximum processing time TP of the logic circuit block is shorter than the cycle time TC of the clock signal CK.
Reduction in operating speed of the logic circuit block is caused by variations in the operating environment, such as increases in the operating temperature, decreases in the power source voltage, and by the effect of variation in the manufacturing process. Variations in the operating environment contributing to the reduction in operating speed may include increases in gate oxide film thickness, increases in gate length, reduction in gate width, decrease in channel ion density, and the like. Logic circuits must meet the predetermined standards even if all of these operating speed reducing factors occur at the same time.
However, each of the logic circuit blocks, which altogether form the logic circuit, has a different function. The logic circuit has integrated therein both critical blocks requiring longer processing time for complex operations and simple circuits for simple operations. Therefore, the problem is that when specifications of the guaranteed operating extent are established based on the worst conditions in the critical blocks, even if the specifications in other logic circuit blocks become excessive, control of the maximum speed of the clock signal CK must be obtained.
The present invention is devised to solve the problems relating to the prior art and provide a clock signal feeding circuit that controls reduction in operating speed due to variation in conditions, and suppresses performance degradation under the worst operating conditions.
To solve the above problems, a first aspect of the present invention is a clock signal feeding circuit for feeding common clock signals to flip-flops that transmit and receive data between a plurality of logic circuit blocks, which form a semiconductor logic circuit, the clock signal feeding circuit comprising: a first delay buffer for feeding the clock signals to a first flip-flop, which passes data to a critical block with the longest processing time among those of the plurality of logic circuit blocks, the clock signals fed using at least one delay element of which variation in delay time resulting from variations in an operating environment or a manufacturing process is less than that of a critical block; and a second delay buffer for feeding the clock signals to a second flip-flop, which receives data from the critical block, the clock signals fed using delay elements of which variation in delay time resulting from an operating environment or a manufacturing process is substantially equal to variation in delay time of the critical block.
In a second aspect of the present invention, the first delay buffer in the first aspect includes a delay element that possesses a capacitor.
In a third aspect of the present invention, the second delay buffer in the first aspect is formed from a delay element that possesses a transistor of which gate length is substantially equal to that of the transistor in the critical block, and the first delay buffer is formed from a delay element that possesses a transistor of which gate length is longer than that of the transistor in the second delay buffer.
In the fourth aspect of the present invention, a clock signal feeding circuit comprises: a first logic circuit block, which forms a semiconductor logic circuit; a second logic circuit block, which forms the semiconductor logic circuit altogether with the first logic circuit block and conducts processing in processing time shorter than that of the first logic circuit block; a first latch circuit, which outputs data to the first logic circuit block; a second latch circuit, which receives data outputted from the first logic circuit block and then outputs data to the second logic circuit block; a clock terminal provided at each of the first and second latch circuits; a clock signal line, which is connected to each of the clock terminals, and to which the clock signals are inputted; a first delay buffer, which is connected between the clock signal line and the first latch circuit, and is formed from a delay element of which variation in processing time that is affected by an operating environment or a manufacturing process is smaller than variation in processing time that is affected by an operating environment or a manufacturing process in the first logic circuit block; and a second delay buffer, which is connected between the clock signal line and the second latch circuit, and is formed from a delay element of which variation in processing time that is affected by an operating environment or a manufacturing process is at least substantially equal to variation in processing time that is affected by an operating environment or a manufacturing process in the first logic circuit block.
In a fifth aspect of the present invention, the first logic circuit block in the fourth aspect is a logic circuit block that requires the longest processing time among those of the plurality of logic circuit blocks, which form the semiconductor logic circuit.
In a sixth aspect of the present invention, the first delay buffer in the fourth aspect includes a delay element that possesses a capacitor.
In a seventh aspect of the present invention, the second delay buffer in the fourth aspect is formed from a delay element that possesses a transistor of which gate length is substantially equal to that of the transistor in the first logic circuit block, and the first delay buffer is formed from a delay element that possesses a transistor of which gate length is longer than that of the transistor in the first logic circuit block.
In an eighth aspect of the present invention, the gate length of the transistor which forms the second delay buffer in the seventh aspect is the smallest among those of the transistors in the semiconductor logic circuit; and the gate length of the delay element forming the first delay buffer is determined based on the rate of variation in the minimum dimension, the cycle time of the clock signal, and the time from which the clock signal is transmitted on the clock signal line (i.e., from the time point at which the clock signal is inputted into the clock signal line to the time point at which the clock signal is inputted into the clock terminal of the latch circuit).
Because the clock signal feeding circuit is thus constructed, the present invention has the following operation.
The clock signals are fed, via the first delay buffer of which variation in delay time is small, to the first FF, which passes data to the critical block that requires the longest processing time among those of the plurality of logic circuit blocks. Further, the clock signals are fed, via the second delay buffer of which variation in delay time is substantially equal to that of the critical block, to the second FF, which receives data from the critical block. With this structure, when the processing time in the critical block increases due to circumstances such as variations in the operating environment, the timing of outputting the data representing the operation result delays, and the timing of feeding the clock signals to the second FF also delays due to the same circumstances. Accordingly, even if circumstances such as variations in the operating environment occur, the second FF receives the operation result outputted from the critical block.
As described above, the first aspect of the present invention comprises the first delay buffer for feeding the clock signals to the first FF, which passes data to the critical block, the clock signals fed using the delay element of which variation in delay time is small, and the second delay buffer for feeding the clock signals to the second FF, which receives data from the critical block, the clock signals fed using the delay element of which variation in delay time is substantially equal to variation in delay time in the critical block. With this structure, when the processing time in the critical block increases due to circumstances such as variations in the operating environment, the timing of feeding the clock signals to the second FF also delays at the same time, the reduction in operating speed due to variation in conditions can be controlled, and performance degradation under the worst operating conditions can be suppressed.
According to the second aspect of the present invention, the first delay buffer in the first aspect includes a delay element that possesses a capacitor, whereby the circuit can be designed simply.
According to the third aspect of the present invention, the second delay buffer in the first aspect is configured from a transistor of which gate length is substantially equal to that of the transistor in the critical block, and the first delay buffer is formed from a transistor of which gate length is longer than that of the transistor in the second delay buffer. With this structure, the clock signal feeding circuit can be designed through processes such as simulation more easily than in the second aspect, which possesses a capacitor, and also offers good accuracy with current manufacturing technology.
The fourth aspect of the present invention includes: the first delay buffer, which is formed from a delay element of which variation in delay time is smaller than variation in delay time in the first logic circuit block and feeds the clock signals to the first latch circuit that output data to the first logic circuit block requiring longer processing time; and the second delay buffer, which is formed from a delay element of which variation in delay time is substantially equal to variation in delay time in the first logic circuit block and feeds the clock signals to the second latch circuit that receives input of the data outputted from the first logic circuit block. With this structure, when the processing time in the first logic circuit block increases due to circumstances such as variations in the operating environment, the clock signal fed to the second latch circuit also delays at the same time, hence the reduction in operating speed due to variation in conditions can be controlled, and performance degradation can be suppressed.
According to the fifth aspect of the present invention, the first logic circuit block in the fourth aspect is a logic circuit block that requires the longest processing time among those of the plurality of logic circuit blocks, which form the semiconductor logic circuit. Therefore, performance degradation in the critical block under the worst operating conditions can be suppressed.
According to the sixth aspect of the present invention, the first delay buffer in the first aspect is formed from the delay element that possesses a capacitor, whereby the circuit can be designed simply.
According to the seventh aspect of the present invention, the second delay buffer in the fourth aspect possesses the transistor of which gate length is substantially equal to that of the transistor in the first logic circuit block, and the first delay buffer possesses the transistor of which gate length is longer than that of the transistor in the first logic circuit block. With this structure, the clock signal feeding circuit with higher accuracy than in the sixth aspect in which a capacitor is used can be obtained with current manufacturing technology.
According to the eighth aspect of the present invention, the gate length of the transistor which forms the second delay buffer in the seventh aspect is the smallest among those of the transistors in the semiconductor logic circuit. Further, the gate length of the transistor which forms the first delay buffer is determined in accordance with variation in the minimum dimension, the cycle time of the clock signal, and the time during which the clock signal is transmitted on the clock signal line. With this structure, the clock signal feeding circuit can be easily designed through processes such as simulation, and good accuracy can be obtained with current manufacturing technology.